In complex multicore System on a Chip (SOC) devices it is important to have a low latency, high throughput messaging system for Inter Processor Communication (IPC) and peer to peer (P2P) communication with very low overhead. Historically, communications have been implemented in a variety of fashions, but without uniformity, with each requiring specific hardware architectures. Two common examples include shared memory or hardware mailboxes.
Shared memory solutions have to deal with coherency issues when one core is attempting to consume data produced by another producer (core). Any coherence operation consumes processing power and adds latency. Most mechanisms also rely on synchronization methods implemented in software such as a semaphore to gate access to shared memory that adds performance penalty. In addition, shared memory is inherently unsecure and susceptible to accidental or intentional corruption.
Direct message passing models provide direct communication between two processor cores using some form of hardware or software “mailbox” that fit a specific need, but and are not flexible for a broader application (such as peer to peer messaging).